1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly, to an input buffer circuit and a control circuit therefor.
2. Description of the Related Art
As the rate for transferring data between semiconductor chips has increased, the problem of a skew occurring between a clock signal and a data signal has become more pronounced. The term "skew" as used herein refers to an asynchronism between/among bits which are read out in parallel. Usually, when there is a skew between a clock signal and a data signal, there is also a skew between two data signals. Accurate data transfer cannot be accomplished with such a skew.
Typically, in applications where high-speed data transfer is required, the signal output timing is adjusted by using DLL (Delay Lock Loop), PLL (Phase Lock Loop), or the like for suppressing a skew due to a phase difference among a number of signals. By the use of such an output timing adjustment, data signals and a clock signal will be in phase with one another, thereby suppressing the skew due to phase difference among the signals.
In other applications where the data transfer rate is even higher, however, there arises another problem; that is, a skew between two signals which occurs when the periods of time, in which the signals change from one state to another, i.e., the transition times of the signals, differ from each other because the signals have been continuously at the same voltage (or logical) level for different periods of time. The longer a signal remains at the same level, the longer the driver for outputting the signal takes for driving the signal, whereby the transition time of the signal is also longer.
Therefore, when a data signal changes from a first data value to a second data value after successive occurrences of the first data value, the transition time of the data signal is relatively long. On the other hand, the transition time of a data signal is relatively short after the data value of the data signal changes successively. Thus, the transition time of a data signal after successive occurrences of the same data value is different from that after successive changes in data value. When two or more data signals have different transition times due to the difference in the period of time for which the same data value has occurred continuously, a skew occurs between the data signals.
FIG. 4 shows a skew occurring between two data signals D1 and D2 while they are transferred between chips. The data signals D1 and D2 have different transition times due to the difference in the period of time for which the same data value has occurred continuously. As shown in FIG. 6, the signals D1 and D2 both rise from an L level to an H level at time T1. The term "H level" as used herein refers to a relatively high signal voltage, and corresponds to the larger logical value in a binary expression, whereas the "L level" as used herein refers to a relatively low signal voltage, and corresponds to the smaller logical value in the binary expression.
Referring to FIG. 6, the data signal D1 rises at T1 from the L level to the H level after successive occurrences of the L level data value. The data signal D2 similarly rises at T1 from the L level to the H level, but after successive changes in data value. Even if the signals D1 and D2 are controlled to start rising at the same time (e.g., time T1) by the output timing adjustment (e.g., an ON/OFF timing adjustment of the driver), there is a difference TSK between the times at which the signals D1 and D2 respectively reach a reference potential Vref.
Still referring to FIG. 6, the data signal D2 changes at time T0 corresponding to the rising edge of the clock CLK, and changes again immediately at time T1 corresponding to the falling edge of the clock CLK. In such a case, if the frequency of the clock CLK is as high as about 100 MHz, for example, the data signal D2 starts transiting to the next data value (a voltage value VH corresponding to the H level), before it reaches a voltage value VL corresponding to the L level. Thus, there occurs a difference dV between the data signal D2 at time T1 and the voltage value VL corresponding to the L level. Due to the difference dV, there occurs the difference TSK between the times at which the signals D1 and D2 respectively reach the reference potential level Vref (Vref is used by the data receiving side for detecting whether the signal is at the H level or at the L level).
Thus there occurs a skew between the data signals D1 and D2 due to the rising time difference TSK between the signals. This problem of the skew occurring due to the difference TSK is more pronounced as the frequency of the clock CLK increases (e.g., to about 100 MHz).
While the former type of skew, which occurs due to the phase difference among a number of signals (e.g., 8 bits), can be suppressed by the above-described output timing adjustment, the latter type of skew, which occurs due to the difference in the transition time resulting from the difference in the period of time for which the signal voltage has remained unchanged, cannot be suppressed by the prior art.